Modern semiconductor circuit components are manufactured by first placing electronic circuit components on semiconductor wafers and then packaging different circuits into circuit component packages. Packages include semiconductor “chips” that are placed in systems with many other chips to create a product such as a personal computer or a network router. At various stages in the manufacturing process, it is important to verify that the components function properly and meet specifications. Testing a component includes, for example, sending a pattern of bits to a component and verifying that the component receives and interprets the pattern correctly. Testing can also include component characterization, which establishes or verifies a set of operating parameters for the component. For example, for a component that performs a binary signaling protocol, it is necessary to guarantee that the component will interpret voltages in certain ranges as ones or zeroes. Typically, components are tested with a specialized piece of equipment called a test system or tester.
Recent improvements in the ability of components to produce a greater range of signaling bandwidths and to operate at higher frequencies have increased the cost and difficulty of testing and characterizing components. In order to test and characterize components, a test system must operate at a frequency at least as high as the operating frequency of the component under test. The test system requires some tester guard band, which is a margin around the tested values required to guarantee the tested values. In the past, it was relatively easy to produce test systems that were faster than the tested components. That is not the case now, as even mass-produced metal oxide semiconductor (“MOS”) components achieve ever greater speeds. High-speed test systems that are capable of exceeding the speeds of the fastest components today are very expensive. As component designers produce faster and faster component designs, it becomes more problematic for potential manufacturers to produce the designs because of the required investment in faster test systems.
FIG. 1 is a block diagram of a prior art high-speed interface 100 of a component A. The high-speed interface 100 is coupled to an interconnect 108, which is an electrical conductor or conductors. The high-speed interface 100 includes a receiver block 104, a transmitter block 102, and a termination block 106. The receiver 104 includes a voltage discriminator element 132, a register element 130, and a receive clock aligner element 128. The voltage discriminator element 132 is a differential comparator that compares the VP (high logic value) and VN (low logic value) voltages values on interconnect 108 to determine what symbol is present (e.g., a “1” or a “0”). The register element 130 is a time discriminator that samples the output of the voltage discriminator element 132 on the rising edge of the CLKRA signal (the receive clock signal of component A), stores it, and drives it as the RA signal (receive signal of component A), to be used by other circuits on the component A. The receive clock aligner element 128 creates the CLKRA signal from the CLKRREF (receive clock reference) reference signal. The receive clock aligner element 128 is typically a phase locked loop (“PLL”) or a delay locked loop (“DLL”) circuit.
The termination block 106 includes two load devices 134a and 134b, coupled to interconnect 108 with one terminal and to the VT supply with the other terminal. A terminal of load device 134a is coupled to a first signal line, in interconnect 108, that provides a VP voltage value and a terminal of load device 134b is coupled to a second signal line, in interconnect 108, that provides a VN voltage value. The termination block 106 further includes a control element 136, which adjusts the resistive value RT of the load devices 134 to match an external reference resistance, RREF.
The transmitter block 102 includes a predriver element 118, two differential driver elements 120 and 122, two current source elements 124 and 126, a current control element 114, a register element 116, and a transmit clock aligner element 112. The register element 116 is a time drive element that samples the TA signal (transmit signal from other circuits on component A) and drives it on the rising edge of the CLKTA signal. The transmit clock aligner element 112 creates the CLKTA signal from the CLKTREF reference signal. The transmit clock aligner element 112 is typically a phase locked loop (“PLL”) or a delay locked loop (“DLL”) circuit. The output of the register element 116 connects to the predriver element 118, which connects to the differential driver elements 120 and 122. Each driver element 120 and 122 is an open drain transistor, and is connected in series with one of the current source elements 124 and 126, respectively. The current control element 114 maintains a sink current of IOL (output low current) in the current source elements using an external reference value IREF. When the transmitter 102 drives a bit, one of the two driver elements 120 and 122 is on, and the other is off.
In an alternate embodiment, the two current source elements 124 and 126 could be merged into a single current source element, with one terminal connecting to the low supply voltage (ground) and the other terminal connecting to the source terminals of the two driver elements 120 and 122. This will be equivalent to the circuit shown in transmitter block 102 since only one of the two driver elements 120 and 122 may be on at any time.
FIG. 2 shows a prior art test system 202 used to characterize and test the transmitter 102 and the receiver 104 of component A. Typically, component A will be mounted on a load board 222, which is a printed circuit board. The testing system 202 and the load board 222 approximately duplicate the environment seen by component A during normal operation. The load board 222 has an interconnect 212 that couples the interface 100 of the component A to the high-speed pin electronics 204 of test system 202. The interconnect 212 has a characteristic impedance ZO which may be the same as, or different from, that of the manufactured system interconnect 108. The interconnect 108 is terminated on one end by termination 214 in high-speed pin electronics 204, and on the other end by termination 106. The high-speed pin electronics 204 include timing circuitry 206 to adjust the drive point and the sample point of signals. The high-speed pin electronics 204 further include voltage/current force/sense circuitry 208 to force and sense voltage values and to force and sense current values. The high-speed pin electronics 204 also include pattern generation circuitry 210 for storing, generating, and comparing test patterns. Typically, the accuracy and resolution of circuitry 206, circuitry 208 and circuitry 210 are very high in order to minimize the uncertainty due to measurement error. As a result, the cost of pin electronic 204 is also very high. This is particularly true in the case in which the component A has high-speed signals, each requiring its own set of pin electronics. The test system 202 must simultaneously provide a high signaling rate, precise timing control, and precise voltage/current control for each signal to be tested.
The test system 202 further includes circuitry that generates reference signals 110 used by component A. The reference signals 110 include IREF, RREF, CLKRREF, and CLKTREF. These reference signals are typically shared across the entire component A. These reference signals 110 often do not need the simultaneous combination of high-speed, voltage/current accuracy and timing accuracy. Therefore, the circuitry necessary to produce the reference signals is relatively easier and cheaper to produce compared to the high-speed pin electronics 204. For example, the RREF signal will typically shift through a small set of discrete values during testing. The IREF signal will typically shift through some range of direct current (“DC”) values during testing. The CLKRREF and CLKTREF signals provide a frequency and phase reference for the component A. The clock frequency will typically shift through a small set of discrete values during testing. The clock phase will typically shift through some range of values during testing. Typically, a component will utilize frequency multiplication, so that the required signaling rate of the CLKRREF and CLKTREF signals is much lower than the signaling rate of the high-speed signals.
Another disadvantage of prior art test systems, such as the high-speed test system 202, is that they cannot be used at every stage of the manufacturing process. The result is more defective components being passed to later stages of the manufacturing process. In a typical manufacturing process, there are at least three possible testing stages: 1) component wafer testing; 2) component package testing; and 3) in-system testing. Component wafer testing determines which components are acceptable to be packaged. Component package testing determines which components are acceptable to be used in a system. In-system testing determines which systems work properly. Usually, components are tested twice, once at the wafer level before packaging, and again after packaging. High-speed testing, however, is only performed after packaging when packages can be placed on a load board such as load board 222. All high-speed testing must be performed with a high-speed test system, such as high-speed test system 202. Typically a high-speed test system performs the most exhaustive testing during the component package test. It is usually not possible to perform component wafer testing at full speed. The final in-system test can be performed at full speed, but must use nominal parameter values because of the difficulty of probing high-speed interconnects within an operating system.
There is a need for a method and apparatus for testing and characterizing high-speed components that does not require an expensive high-speed test system. There is also a need for a method and apparatus for providing more uniform testing at each stage of the manufacturing process.